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ISL97522
Data Sheet December 13, 2006 FN7445.0
4-Channel TFT-LCD Supply
The ISL97522 represents a 4-channel supply control IC for use in large panel TFT-LCD displays. Supporting inputs from 4.5V to 13V, the ISL97522 includes a boost controller to achieve the required AVDD output voltage. Both VON and VOFF are generated using off-chip charge-pumps which are then post regulated using on-board LDO controllers. The logic supply is generated using an internal nonsynchronous buck controller. This controller runs at 180 out of phase with the AVDD supply to minimize input noise. The AVDD, VOFF, and VON outputs are automatically sequenced as AVDD, VOFF, and VON. By using an optional external series transistor with AVDD (Q1), the start-up sequence can be adjusted to VOFF, AVDD and then VON. A VON slicing circuit is also included to reduce LCD flicker. The ISL97522 also incorporates a fault protection circuit that can disable the IC and turn off all outputs when an output short is detected. (Note that to protect AVDD a single external transistor is required).
Features
* 4.5V to 13V input * Boost controller for AVDD * Regulated LDOs for VOFF and VON * Buck controller for logic output * VON slicing circuit * Fully fault-protected * Programmable sequence * 1MHz switching frequency * 38 Ld QFN package * Pb-free plus anneal available (RoHS compliant)
Applications
* LCD-TVs (up to 50"+) * LCD monitors (15"+) * Industrial/medical LCD displays
Ordering Information
PART NUMBER (Note) PART MARKING TAPE & PACKAGE REEL (Pb-Free) PKG. DWG. #
Pinout
ISL97522 (38 LD QFN) TOP VIEW
33 CDLY 32 VCC2 31 FBP 30 VREF 29 ACGND 28 NC 27 DRVP THERMAL PAD 26 NC 25 VDCP 24 VDC 23 ISADJL 22 CINTL 21 ILADJL 20 PBL ISINB 13 VIN 14 EN 15 VHIL 16 LX 17 DRVL 18 PGNDP 19 37 COM 36 DRN 38 SRC 35 ENL 34 CTL
ISL97522IRZ-TK ISL 97522IRZ ISL97522IRZ-T ISL 97522IRZ
13" 38 Ld QFN L38.5x7B (1k pcs) 13" 38 Ld QFN L38.5x7B (4k pcs)
DRVN 1 DELB 2 FBN 3 VCC1 4 FBB 5 ISADJB 6 ILADJB 7 CINTB 8 DRVB 9 PGNDB 10 VHIB 11 NC 12
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97522
Absolute Maximum Ratings (TA = +25C)
Maximum Pin Voltages, all pins except below . . . . . . . . . . . . . . 6.5V VIN,EN,ENL,LX,VHIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V VDELB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V VDRVP, VSINB, SRC, COM, DRN . . . . . . . . . . . . . . . . . . . . . . .36V VDRVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V
Thermal Information
Thermal Resistance 38 Ld QFN Package (Notes 1, 2). . . . . JA (C/W) 33 JC (C/W) 4.5
Operating Conditions
Input Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 13V Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . +15V to +25V VON Output Range, VON . . . . . . . . . . . . . . . . . . . . . . . +15V to +32V VOFF Output Range, VON . . . . . . . . . . . . . . . . . . . . . . . . -15V to -5V Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2x10F Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3H to 10H Output Capacitance, COUT . . . . . . . . . . . . . . . . . . . . . . . . . . 4x10F Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3H to 10H Operating Ambient Temperature Range . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL VIN IS Input Voltage
VIN = 5V, AVDD = 15V, VON = 20V, VOFF = -9V, VLOGIC = 3V, Over Temperature from -40C to +85C CONDITION MIN TYP MAX UNIT
DESCRIPTION
4.5 EN = 0, ENL = 0 EN = ENL = 1, switching 3 15 850 TA = +25C 1.192 1.190 1000 1.215 1.215
13.2
V mA mA
Sum Quiescent Current into Vin
FOSC VREF
Oscillator Frequency Reference Voltage
1100 1.235 1.237
kHz V V
AVDD VFBB Feedback Reference Voltage TA = +25C 1.195 1.193 VF_FBB DMIN DMAX Eff IFBB RLINEB RLOADB RONB FBB Fault Trip Point Minimum Duty Cycle Maximum Duty Cycle Boost Efficiency FBB Input Bias Current Line Regulation Load Regulation Gate Drive on Resistance CINT = 2.2nF, VIN = 4.5V to12V, IO =100mA CINT = 2.2nF, VIN = 5V, IAVDD = 100mA to 350mA Pull-up Pull-down 80 VFBB falling 0.85 1.208 1.208 0.9 19 86 90 25 0.01 0.03 3.6 1.9 0.25 0.25 1.221 1.223 0.95 25 V V V % % % nA %/V %
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ISL97522
Electrical Specifications
PARAMETER IPEAKB VIN = 5V, AVDD = 15V, VON = 20V, VOFF = -9V, VLOGIC = 3V, Over Temperature from -40C to +85C CONDITION Source Sink IISADJB IILADJB VON LDO VFBP FBP Regulation Voltage IDRVP = 0.2mA,TA = +25C IDRVP = 0.2mA VF_FBP IFBP RLOADP IDRVP IL_DRVP VOFF LDO VFBN FBN Regulation Voltage IDRVN = 0.2mA,TA = +25C IDRVN = 0.2mA VF_FBN IFBN RLOADN IDRVN IL_DRVN VLOGIC VFBL FBL Regulation Voltage TA = 25C 1.178 1.176 DMIN DMAX EFFL IFBL ILINEL ILOADL RONL Minimum Duty Cycle Maximum Duty Cycle Logic Buck Efficiency FBL Input Bias Current VLOGIC Line Regulation VLOGIC Load Regulation Gate Drive on Resistance CINT = 2.2nF, VIN = 5V to 12V CINT = 2.2nF, ILOGIC = 100mA to 450mA Pull-up Pull-down IPEAKL Peak Drive Current Source Sink IISADJL IILADJL ISADJB Output Current ILADJB Output Current RSADJB = 30k RLADJB = 30k 1.2 1.2 20 85 90 20 0.03 0.1 3.6 1.9 600 900 15 17 0.25 0.5 1.222 1.224 V V % % % nA %/V % mA mA A A FBN Fault Trip Point FBNInput Bias Current VOFF Load Regulation DRVN Source Current Max DRVN Leakage Current VFBN rising VFBN = 0.2V I(VOFF) = 0mA to 20mA VFBN = 0.3V, VDRVN = -6V VFBN = 0V, VDRVN = -20V 2 0.186 0.183 0.45 0.213 0.213 0.5 40 0.4 4 0.4 5 0.85 0.24 0.243 0.55 V V V nA % mA A FBP Fault Trip Point FBP Input Bias Current VON Load Regulation DRVP Sink Current Max DRVP Leakage Current VFBP falling VFBP = 1.35V I(VON) = 0mA to 20mA VFBP = 1.1V, VDRVP = 25V VFBP = 1.5V, VDRVP = 35V 2 1.176 1.174 0.82 1.2 1.2 0.87 150 0.5 4 0.3 2 0.75 1.224 1.226 0.92 V V V nA % mA A ISADJB Output Current ILADJB Output Current RSADJB = 30k RLADJB = 30k 10 10 MIN TYP 600 900 15 17 25 25 MAX UNIT mA mA A A
DESCRIPTION Peak Drive Current
VON -SLICE CIRCUIT ILEAKCTL tDrise CTL Input Leakage Current CTL to OUT Rising Prop Delay CTL = AGND or VIN 1k from DRN to 8V, VCTL = 0V to 3V step, no load on OUT, measured from VCTL = 1.5V to OUT = 20% -1 100 1 A ns
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ISL97522
Electrical Specifications
PARAMETER tDfall VIN = 5V, AVDD = 15V, VON = 20V, VOFF = -9V, VLOGIC = 3V, Over Temperature from -40C to +85C CONDITION 1k from DRN to 8V, VCTL = 3V to 0V step, no load on OUT, measured from VCTL = 1.5V to OUT = 80% MIN TYP 100 MAX UNIT ns
DESCRIPTION CTL to OUT Falling Prop Delay
VSRC ISRC
SRC Input Voltage Range SRC Input Current Start-up sequence not completed Start-up sequence completed 0.2 150 5 30 400 1000
30 1.25 250 14 60 1800
V mA A
RONSRC RONDRN RONCOM SEQUENCING tON tSS tDEL1 tDEL2 tDEL3 IDELB_ON
SRC On Resistance DRN On Resistance COM to GND On Resistance
Start-up sequence completed Start-up sequence completed Start-up sequence not completed
Turn On Delay Soft-start Time Delay Between AVDD and VOFF Delay Between VON and VOFF Delay Between VOFF and Delayed VBOOST
CDLY = 0.22F CDLY = 0.22F CDLY = 0.22F CDLY = 0.22F CDLY = 0.22F 35 1.2
30 2 10 17 10 50 1.6 65 2 500
ms ms ms ms ms A K nA
DELB Pull-Down Current or Resistance VDELB > 0.9V when Enabled by the Start-Up VDELB < 0.9V Sequence DELB Pull-Down Current or Resistance VDELB < 20V when Disabled
IDELB_OFF
FAULT DETECTION TFAULT OT LOGIC VHI VLO ILOW IHIGH Logic High Threshold Logic Low Threshold Logic Low Bias Current Logic High Bias Current 16 0.1 23 30 2.2 0.8 V V A A Fault Time Out Over-temperature Threshold CDLY = 0.22F 50 140 ms C
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FN7445.0 December 13, 2006
ISL97522 Typical Performance Curves
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 500 1000 1500 2000 2500 IAVDD (mA) VIN = 12V, AVDD = 17V VIN = 5V, AVDD = 12V LOAD REGULATION (%) 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 0 500 1000 1500 2000 2500 IAVDD (mA) VIN = 12V, AVDD = 17V VIN = 5V, AVDD = 12V
FIGURE 1. BOOST AVDD EFFICIENCY
FIGURE 2. BOOST AVDD LOAD REGULATION
17.04 17.02 VO = 17V EFFICIENCY (%) 17 AVDD(V) 16.98 16.96 16.94 16.92 16.9 16.88 0 2 4 6 8 VIN (V) 10 12 14 16
100 90 80 70 60 50 40 30 20 10 0 0 500 1000 1500 2000 2500 ILOGIC (mA) VIN = 12V, VLOGIC = 3V VIN = 5V, VLOGIC = 3V
FIGURE 3. BOOST AVDD LINE REGULATION
FIGURE 4. BUCK VLOGIC EFFICIENCY
0 LOAD REGULATION (%) -0.2 -0.4 -0.6 -0.8 -1 -1.2 VIN = 12V, VLOGIC = 3V VIN = 5V, VLOGIC = 3V VON (V)
19.75 19.74 19.73 19.72 19.71 19.7 19.69 19.68 19.67 0 500 1000 1500 2000 2500 19.66 0 5 10 15 IVON (mA) 20 25 VON = 20V
ILOGIC (mA)
FIGURE 5. BUCK VLOGIC LOAD REGULATION
FIGURE 6. VON LOAD REGULATION
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ISL97522 Typical Performance Curves
(Continued)
-8.875 -8.880 VOFF (V) -8.885 -8.890 -8.895 -8.900 -8.905 VOFF = -9V CH1 = COM (10V/DIV)
CH2 = CTL (2V/DIV) 0 5 10 15 IVOFF (mA) 20 25
FIGURE 7. VOFF LOAD REGULATION
FIGURE 8. 4ms/DIV VON SLICE CIRCUIT OPERATION
CDLY
CDLY
EN AVDD VLOGIC VON
AVDD
VOFF
FIGURE 9. START-UP SEQUENCE
FIGURE 10. START-UP SEQUENCE
AVDD (BOOST) VLOGIC (BOOST MODE) IIN IIN
FIGURE 11. IN RUSH CURRENT
FIGURE 12. IN RUSH CURRENT
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ISL97522 Typical Performance Curves
(Continued)
VLOGIC (BUCK MODE) AVDD (BUCK) IIN IIN
FIGURE 13. IN RUSH CURRENT
FIGURE 14. IN RUSH CURRENT
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FN7445.0 December 13, 2006
ISL97522 Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PIN NAME DRVN DELB FBW VCC1 FBB ISADJB ILADJB CINTB DRVB PGNDB VHIB NC ISINB VIN EN VHIL LX DRVL PGNDP FBL ILADJL CINTL ISADJL VDC VDCP NC DRVP NC ACGND VREF FBP CC2 CDLY CTL ENL DRN COM SRC Low noise signal ground. Bandgap voltage bypass terminal; bypass with a 0.1F to analog GND; can be used as charge pump reference. Positive LDO voltage feedback input pin; regulates to 1.2V nominal. Supply input, connect to VIN. With a capacitor connect from this pin to GND, sets the delay time for start-up sequence and fault detection timeout. Input control for switch output. Enable pin for VLOGIC high enable; low disabled. Lower reference voltage for switch output. Switch output; when CTL = 1, COM is connected to SRC through a 15 resistor, when CT: = 0, COM is connected to DRN through a 30 resistor. Upper reference voltage for switch output. Positive LDO base drive; open drain of an internal N-Channel MOSFET. Sense the drain voltage of the external N-channel FET and connected to the internal current limit comparator. Main supply input. Enable pin; high enable, low disabled. VLOGIC boost strap mode. VLOGIC switch connection. Gate driver output for external N-channel switch. Power GND. VLOGIC regulator voltage feedback pin; regulates to 1.2V nominal. With resistor connected from this pin to GND sets the current limit of the external N-channel FET. VLOGIC integrator output, connect 2.2nF to analog GND. Current feedback adjust for VLOGIC. Positive supply for all internal analog circuits. Positive supply for external N-Channel FET gate drives. PIN DESCRIPTION Negative LDO base drive; open drain of an internal P-Channel MOSFET. Active low control output for optional delay control for external AVDD P-Channel FET; when fault is detected, this pin goes to high. Negative LDO voltage feedback input pin; regulates to 0.2V nominal. Supply input, connect to VIN. AVDD regulator voltage feedback input pin; regulates to 1.2V nominal. Current feedback adjust for AVDD. With a resistor connected from this pin to GND sets the current limit of the external N-channel FET for AVDD. AVDD integrator output, connect 2.2nF to analog GND. Gate driver output for the external N-Channel switch. Power GND for AVDD. Internal Drive of Boost controller, Connect to VDCP.
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FN7445.0 December 13, 2006
ISL97522 Typical Application Diagram
VN C25 0.1F D21 C24 0.1F L1 6.8H VIN C2 ION FX3 10FX2 C1 VIN ISINB DRVB BOOST CONTROLLER FBB VHIB INTERNAL SUPPLY DRVN FBN POWER ON SEQUENCING VOFF LDO VREF C25 1F DRVP VCC2 VON LDO FBP R11 12k R23 1k VP R4 3k R21 20k Q11 R12 237k 25V VON C15 1F VDCP Q1 R1 12k VN R3 3k Q21 R22 104k C20 4.7F -8V VOFF R2 140k R9 1M C16 0.01F R8 300k VSW C11 0.1F D1 VBOOST D11 VP
Q3
15V AVDD C9 0.01F
C30 4.7NF R10 10k CINTB R20 30k R19 30k VDCP ISADJB ILADJB
C23 4.7F
VDC C24 4.7F CDLY
C7 220nF EN R29 10k
CONTROL INPUT VSW
CTL
SRC COM
DELB
FAULT PROTECTION
VON SLICE DRN
TO GATE DRIVER R21 L2 6.8F C3 D2 10FX4F
R22 68k C32 100nF
VIN Q2 VCCL CLOCK/ TIMING DRVL LX FBL BUCK CONTROLLER VHIL C28 0.47
VLOGIC R12 210k
ENL R28 10k PGNDB PGNDP ACGND R15 30k C27 4.7nF ISADJL CINTL R17 2k ILADJL R16 30k
R13 118k
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FN7445.0 December 13, 2006
ISL97522 Applications Information
The ISL97522 provides a multiple output power supply solution for TFT-LCD applications. The system consists of a high efficiency boost controller, two low cost linear-regulator controllers (VON and VOFF) and a buck reglator (VLOGIC). Table 1 below lists the recommended components.
TABLE 1. RECOMMENDED COMPONENTS DESIGNATION C1, C2, C3 C20 C15 D1 D11, D12, D21 L1 Q1,Q2 DESCRIPTION 10F, 16V, X7R ceramic capacitor (1206) TDK C3216X7R1C106M 4.7F, 16V X5R ceramic capacitor (1206) TDK C3216X5R1A475K 1F, 25V X7R ceramic capacitor (1206) TDK C3216X7R1E105K 1A 20V low leakage schottky rectifier (CASE 457-04) ON SEMI MBRM120ET3 200mA 30V schottky barrier diode (SOT-23) Fairchild BAT54S 6.8mH 4.6A inductor Coilcraft DO3316P-682ML 6.3A 30V single N-Channel logic level PowerTrench MOSFET (SOT-23) Fairchild FDC655AN -2A -30V single P-Channel logic level PowerTrench MOSFET (SuperSOT-3) Fairchild FDN360P 200mA 40V PNP amplifier (SOT-23) Fairchild MMBT3906 200mA 40V NPN amplifier (SOT-23) Fairchild MMBT3904
AVDD Converter
The main boost converter is a current mode PWM controller operating at a fixed frequency. The 1MHz switching frequency enables the use of low profile inductor and multilayer ceramic capacitors, which results in a compact, low-cost power system for LCD panel design. The AVDD converter can operate in continuous or discontinuous inductor current mode. The ISL97522 is designed for continuous current mode, but it can also operate in discontinuous current mode at light load. In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by (in boost mode):
A VDD 1 --------------- = -----------1-D V IN (EQ. 1)
where D is the duty cycle of switching MOSFET. Figure 15 shows the function diagram of the boost controller. It uses a summing amplifier architecture consisting of GM stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 200k is recommended. The boost converter output voltage is determined by the following equation:
R1 + R2 A VDD = -------------------- x V FBB R1 (EQ. 2)
Q3
Q11 Q21
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FN7445.0 December 13, 2006
ISL97522
VREF
REFERENCE GENERATOR
VIN OSCILLATOR OSC
SLOPE COMPENSATION
VBOOST
FBB CINTB GM AMPLIFIER
PWM LOGIC CONTROLLER
DRVB BUFFER ISADJ ISIN
CURRENT AMPLIFIER SHUTDOWN & STARTUP CONTROL UVLO COMPARATOR CURRENT LIMIT COMPARATOR CURRENT LIMIT REF GENERATOR ILADJ
FIGURE 15. FUNCTION DIAGRAM OF THE BOOST CONTROLLER
The internal current limit circuitry is shown in Figure 16. The circuit senses the voltage across the RDS(ON) when the MOSFET is on; then compare it to the internal voltage reference to realize the current limit. The internal voltage reference is generated by a 10mA current and any additional current set at ILADJB pin flowing through an 8k resistor. The voltage reference is based on the following equation:
V ILADJB V THRESHOLD = ----------------------- + 10A x 8K R1 (EQ. 3)
VDD 10A VREF 1k R1 ILADJB 8k + ISINB
LX
LOGIC CONTROLLER
Where VILADJB is the voltage at pin ILADJ. Where VISAD is the voltage at pin ISAD.
V ISAD = V REF - V BE - 1K x I SAD V ISAD I SAD = ---------------R1
DRVB
FIGURE 16. CURRENT LIMIT BLOCK DIAGRAM (EQ. 4)
Hence the maximum output current is determined by the following equation:
V IN V THRESHOLD I L I OMAX = --------------------------------------- - -------- x --------R DSON 2 VO (EQ. 5)
Where VBE 0.7V The external resistor R1 should be chosen in the order of 100K to generate A of current.
Where IL is the peak to peak inductor ripple current, and is set by:
V IN D I L = --------- x ---L fS (EQ. 6)
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ISL97522
fS is the switching frequency; D is the duty cycle.
V O - V IN D = ----------------------VO (EQ. 7)
Boost Inductor
A 6.8H inductor is recommended. The inductor must be able to handle the following average and peak current:
IO I LAVG = -----------1-D I L I LPK = I LAVG + -------2 (EQ. 8)
To overcome the variation in external LX driver RDS(ON) , an input is provided (ILADJ) to accommodate 5 different bands of RDS(ON) by using 5 different selection resistors. Internally, the ILADJ resistor adjusts two things: 1.the current limit; 2.the current feedback being used. This keeps the dc-dc loop stable and the current limit the same over a wide range of external drive FETs. Alternatively, the current limit can be changed for the same FET by varying the resistor. This would affect the stability of the system somewhat (because the current feedback changes) but be selected appropriately to accommodated the change. The integrator loop should keep the load regulation within limits as long as it doesn't run out of dynamic adjustment range when current feedback gets larger than intended. This could be determined by measuring how close to the upper clamp limit the voltage on the Cint pin voltage gets under maximum load current. Here are the resistor settings on ILADJ which select the five RDS(ON) ranges: 1/ 0ohms (Cfb factor 1, "Cfb" are the relative current feedback factors) 2/ 30K 3/ 83K (Cfb factor 1/1.8) (Cfb factor 1/3.3)
(EQ. 9)
BOOST MOSFET
Due to the parasitic inductance of the trace, the MOSFET will experience spikes higher that the output voltage when the MOSFET turns off. Thus, a MOSFET with enough voltage margin is needed. The RDS(ON) of the MOSFET is critical for power dissipation and current limit. A MOSFET with low RDS(ON) is desired to get high efficiency and output current, but very low RDS(ON) will reduce the loop stability. A MOSFET with 20m to 50m RDS(ON) is recommended. Some recommended MOSFETs are shown in Table 2.
TABLE 2. RECOMMENDED MOSFETs PART NUMBER FDC655AN FDS4488 Si7844DP SI6928DQ MANUFACTURER Fairchild Semiconductor Fairchild Semiconductor Vishay Vishay FEATURE 6.3A, 30V, RDS(ON) = 23m 7.9A, 30V, RDS(ON) = 22m 10A, 30V, RDS(ON) = 22m 20A, 30V, RDS(ON) = 30m
Rectifier Diode
A high-speed diode is desired due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The rectifier diode must meet the output current and peak inductor current requirements.
4/ 182K (Cfb factor 1/5.7) 5/ >370K (Cfb factor 1/10) 1/ sets maximum internal current feedback and minimum ILimit, used for low Ron fets. 5/ sets minimum internal current feedback and maximum ILimit, used for large Ron fets. The Current limit factors should be the inverse of the Cfb values.
Output Capacitor
The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor.
IO V O - V IN 1 V RIPPLE = I LPK x ESR + ----------------------- x --------------- x ---VO C OUT f S (EQ. 10)
Input Capacitor
The input capacitor is used to supply the current to the converter. It is recommended that CIN be larger than 10F. The reflected ripple voltage will be smaller with larger CIN. The voltage rating of input capacitor should be larger than maximum input voltage.
For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage.
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ISL97522
PI mode CINT (C23) and RINT (R10)
The IC is designed to operate with a minimum C23 capacitor of 4.7nF and a minimum C2 (effective) = 10F. Note that, for high voltage AVDD, the voltage coefficient of ceramic capacitors (C2) reduces their effective capacitance greatly; a 16V 10F ceramic can drop to around 3F at 15V. To improve the transient load response of AVDD in PI mode, a resistor may be added in series with the C23 capacitor. The larger the resistor the lower the overshoot but at the expense of stability of the converter loop - especially at high currents. With L = 10H, AVDD = 15V, C23 = 4.7nF, C2 (effective) should have a capacitance of greater than 10F. RINT (R7) can have values up to 5k for C2 (effective) up to 20F and up to 10K for C2 (effective) up to 30F. Larger values of RINT (R7) may be possible if maximum AVDD load currents less than the current limit are used. To ensure AVDD stability, the IC should be operated at the maximum desired current and then the transient load response of AVDD should be used to determine the maximum value of RINT controller function diagrams are shown in Figures 17, and 18, respectively.
AVDD ISINB 0.1F 0.9V PG_LDOP + LDO_ON CP (TO 36V) RBP 3k DRVP FBP + GMP 1 : Np RP1 RP2 0.1F VON (TO 35V) CON
36V ESD CLAMP
FIGURE 17. VON FUNCTION BLOCK DIAGRAM
Operation of the DELB Output Function
An open drain DELB output is provided to allow the boost output voltage, developed at C2 (see application diagram), to be delayed via an external switch (Q3) to a time after the VBOOST supply and negative VOFF charge pump supply have achieved regulation during the start-up sequence shown in Figure 21. This then allows the AVDD and VON supplies to start-up from 0V instead of the normal offset voltage of VIN-VDIODE (D1) if Q3 were not present. When DELB is activated by the start-up sequencer, it sinks 50A allowing a controlled turn-on of Q3 and charge-up of C9. C16 can be used to control the turn-on time of Q3 to reduce inrush current into C9. The potential divider formed by R9 and R8 can be used to limit the VGS voltage of Q3 if required by the voltage rating of this device. When the voltage at DELB falls to less than 0.6V, the sink current is increased to ~1.2mA to firmly pull DELB to 0V. The voltage at DELB is monitored by the fault protection circuit so that if the initial 50A sink current fails to pull DELB below ~0.6V after the start-up sequencing has completed, then a fault condition will be detected and a fault time-out ramp will be initiated on the CDEL capacitor (C7).
Calculation of the Linear Regulator Base-Emitter Resistors ( RBP and RBN)
For the pass transistor of the linear regulator, low frequency gain (Hfe) and unity gain freq. (fT) are usually specified in the datasheet. The pass transistor adds a pole to the loop transfer function at fp = fT/Hfe. Therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high frequency low gain switching transistor. Further improvement can be obtained by adding a base-emitter resistor RBE (RBP, RBL, RBN in the Functional Block Diagram), which increase the pole frequency to: fp = fT*(1+ Hfe *re/RBE)/Hfe, where re = KT/qIc. So choose the lowest value RBE in the design as long as there is still enough base current (IB) to support the maximum output current (IC). We will take as an example the VON linear regulator. If a
Fairchild MMBT3906 PNP transistor is used as the external pass transistor, Q11 in the application diagram, then for a maximum VON operating requirement of 50mA the data sheet indicates HFE_min = 30.
The base-emitter saturation voltage is: Vbe_max = 0.7V. For the ISL97522, the minimum drive current is: I_DRVP_min = 2mA. The minimum base-emitter resistor, RBP, can now be calculated as: RBP_min = VBE_max/(I_DRVP_min - Ic/Hfe_min) = 0.7V/(2mA - 50mA/30) = 2.1k This is the minimum value that can be used - so, we now choose a convenient value greater than this minimum value; say 3K. Larger values may be used to reduce quiescent current, however, regulation may be adversely affected, by supply noise if RBP is made too high in value.
Linear-Regulator Controllers (VON, VOFF)
The ISL97522 includes two independent linear-regulator controllers, in which one is a positive output voltage (VON), and one is negative. The VON and VOFF linear-regulator
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ISINB 0.1F
Set-Up LDOs Output Voltage
Refer to Typical Application Diagram, the output voltages of VON, VOFF, and VLOGIC are determined by Equations 11 and 12:
R 12 V ON = V FBP x 1 + --------- R 11 R 22 V OFF = V FBN + --------- x ( V FBN - V REF ) R
21
CP (TO -26V) LDO_OFF PG_LDON 0.4V FBN 1 : Nn + VREF RN2 0.1F
(EQ. 11)
(EQ. 12)
Charge Pump
RN1 VOFF (TO -20V)
+ GMN 36V ESD CLAMP
DRVN RBN 3k
COFF
To generate an output voltage higher than AVDD, single or multi stages of charge pumps are needed. The number of stage is determined by the input and output voltage. For positive charge pump stages:
V OUT + V CE - V INPUT N POSITIVE ------------------------------------------------------------V INPUT - 2 x V F (EQ. 13)
FIGURE 18. VOFF FUNCTION BLOCK DIAGRAM
The VON power supply is used to power the positive supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the switch node (LXB) of the AVDD converter, followed by a low dropout linear regulator (LDO_ON). The LDO_ON regulator uses an external PNP transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 5mA output current, which is sufficient for up to 50mA or more output current under the low dropout condition (forced beta of 10). Typical VON voltage supported by the ISL97522 ranges from +15V to +36V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 16.7% below the 1.2V reference. The VOFF power supply is used to power the negative supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the switch node (LXB) of the AVDD converter, followed by a low dropout linear regulator (LDO_OFF). The LDO_OFF regulator uses an external NPN transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 5mA output current, which is sufficient for up to 50mA or more output current under the low dropout condition (forced beta of 10). Typical VOFF voltage supported by the ISL97522 ranges from -5V to -25V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 20% above the 1.0V reference level.SetUp LDOs Output Voltage.
where VCE is the dropout voltage of the pass component of the linear regulator. It ranges from 0.3V to 1V depending on the transistor. VF is the forward-voltage of the charge pump rectifier diode. The number of negative charge pump stages is given by:
V OUTPUT + V CE N NEGATIVE -----------------------------------------------V INPUT - 2 x V F (EQ. 14)
To achieve high efficiency and low material cost, the lowest number of charge pump stages, which can meet the above requirements, is always preferred.
Charge Pump Output Capacitors
A ceramic capacitor with low ESR is recommended. With ceramic capacitors, the output ripple voltage is dominated by the capacitance value. The capacitance value can be chosen by Equation 15.
I OUT C OUT -----------------------------------------------------2 x V RIPPLE x f OSC (EQ. 15)
Where fSOC is the switching frequency.
High Charge Pump Output Voltage (>36V) Applications
In the applications where the charge pump output voltage is over 36V, an external npn transistor need to be inserted into between DRVP pin and base of pass transistor Q3 as shown in Figure 19; or the linear regulator can control only one stage charge pump and regulate the final charge pump output as shown in Figure 20.
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The following equation gives the boundary between discontinuous and continuous boost operation. For continuous operation (LX switching every clock cycle) we require that: I(AVDD_load) > D*(1-D)*VIN/(2*L*FOSC)
Q3 NPN CASCODE TRANSISTOR ISL97522 VON
CHARGE PUMP VIN OUTPUT OR AVDD 3k DRVP
where the duty cycle, D = (AVDD - VIN)/AVDD For example, with VIN = 5V, FOSC = 1.0MHz and AVDD = 12V we find continuous operation of the boost converter can be guaranteed for: L = 10H and I(AVDD) > 61mA
FBP
L = 6.8H and I(AVDD) > 89mA L = 3.3H and I(AVDD) > 184mA
Buck Converter
FIGURE 19. CASCODE NPN TRANSISTOR CONFIGURATION FOR HIGH CHARGE PUMP OUTPUT VOLTAGE (>36V)
The buck converter is the step down converter, which supplies the current to the logic circuit of the LCD system. In the continuous current mode, the relationship between input voltage and output voltage is as following:
LX 0.1F AVDD
0.1F 3k DRVP Q3 0.1F
V LOGIC ------------------- = D V IN
(EQ. 16
0.1F VON
0.47F ISL97522
0.1F
(>36V)
Where D is the duty cycle of the switching MOSFET. Because D is always less than 1, the output voltage of buck converter is lower than input voltage.
0.22F FBP
The Feedback Resistors
The buck converter output voltage is determined by the following equation:
FIGURE 20. THE LINEAR REGULATOR CONTROLS ONE STAGE OF CHARGE PUMP
R 12 + R 13 V LOGIC = -------------------------- x V FBL R 13
(EQ. 17)
Discontinuous/Continuous Boost Operation and its Effect on the Charge Pumps
The ISL97522 VON and VOFF architecture uses LX switching edges to drive diode charge pumps from which LDO regulators generate the VON and VOFF supplies. It can be appreciated that should a regular supply of LX switching edges be interrupted, for example during discontinuous operation at light AVDD boost load currents, then this may affect the performance of VON and VOFF regulation depending on their exact loading conditions at the time. To optimize VON/VOFF regulation, the boundary of discontinuous/continuous operation of the boost converter can be adjusted, by suitable choice of inductor given VIN, VOUT, switching frequency and the AVDD current loading, to be in continuous operation.
Where R12 and R13 are the feedback resistors of buck converter to set the output voltage Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 300 is recommended.
Buck Converter Input Capacitor
The capacitor should support the maximum AC RMS current which happens when D = 0.5 and maximum output current.
I acrms ( C IN ) = D ( 1 - D ) IO (EQ. 18)
Where IO is the output current of the buck converter.
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Buck Inductor An inductor value in the range 3.3-10H is recommended for the buck converter. Besides the inductance, the DC resistance and the saturation current should also be considered when choosing buck inductor. Low DC resistance can help maintain high efficiency, and the saturation current rating should be at least maximum output current plus half of ripple current. Buck MOSFET The principle to select Buck MOSFET is similar to that of Boost. The voltage of stress of buck converter should be maximum input voltage plus reasonable margin, and the current rating should be over the maximum output current. The rDS(ON) of this MOSFET should be in the range from 20m to 50m. Rectifier Diode (Buck Converter) A Schottky diode is recommended due to fast recovery and low forward voltage. The reverse voltage rating should be higher than the maximum input voltage. The average current should be as the following equation,
I AVG = ( 1 - D )*I O (EQ. 19)
minimum load can be adjusted by the feedback resistors to FBL. The bootstrap capacitor can only be charged when the higher side MOSFET is off. If the load is too light which can not make the on time of the low side diode be sufficient to replenish the boot strap capacitor, the MOSFET can't turn on. Hence there is minimum load requirement to charge the bootstrap capacitor properly.
Start-Up Sequence
Figure 21 shows a detailed start-up sequence waveform. For a successful power-up, there should be six peaks at VCDLY. When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled. If EN is L, the device is powered down. If EN is H, and the input voltage (VIN) exceeds 2.5V, an internal current source starts to charge CDLY to an upper threshold using a fast ramp followed by a slow ramp. If EN is low at this point, the CDLY ramp will be delayed until EN goes high. The first four ramps on CDLY (two up, two down) are used to initialize the fault protection switch and to check whether there is a fault condition on CDLY or VREF. If a fault is detected, the outputs and the input protection will turn off and the chip will power down. If no fault is found, CCDLY continues ramping up and down until the sequence is completed. During the second ramp, the device checks the status of VREF and over temperature. Initially the boost is not enabled so VBOOST rises to VINVDIODE through the output diode. Hence, there is a step at VBOOST during this part of the start-up sequence. If this step is not desirable, an external PMOS FET can be used to delay the output until the boost is enabled internally. The delayed output appears at AVDD. VBOOST soft-starts at the beginning of the third ramp. The soft-start ramp depends on the value of the CDLY capacitor. For CDLY of 220nF, the soft-start time is ~2ms. VOFF turns on at the start of the fourth peak. At the fifth peak, the open drain o/p DELB goes low to turn on the external PMOS Q3 to generate a delayed VBOOST output. VON is enabled at the beginning of the sixth ramp. AVDD, VOFF, DELB and VON are checked at end of this ramp. Vlogic's start-up is controlled by ENL. When ENL is L, Vlogic is off, and when ENL is H, VLOGIC is on.
Where IO is the output current of buck converter. Output Capacitor (Buck Converter) Four 10F or two 22F ceramic capacitors are recommended for this part. The overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer. PI Loop Compensation (Buck Converter) The buck converter of ISL97522 can be compensated by a RC network connected from CINTL pin to ground. C27 = 4.7nF and R17= 2k RC network is used in the demo board. The larger value resistor can lower the transient overshoot, however, at the expense of stability of the loop. The stability can be optimized in a similar manner to that described in the section on "PI Loop Compensation (Boost Converter)".
Bootstrap Capacitor (C28)
This capacitor is used to provide the supply to the high driver circuitry for the buck MOSFET. The bootstrap supply is formed by an internal diode and capacitor combination. A 1F is recommended for ISL97522. A low value capacitor can lead to overcharging and in turn damage the part. If the load is too light, the on-time of the low side diode may be insufficient to replenish the bootstrap capacitor voltage. In this case, if VIN-VBUCK < 1.5V, the internal MOSFET pull-up device may be unable to turn-on until VLOGIC falls. Hence, there is a minimum load requirement in this case. The
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FAULT DETECTED NORMAL OPERATION
VON SOFT-START
AVDD, SOFT-START
VCDLY
EN
ENL VLOGIC
VREF VBOOST
tON tOS
VOFF
tDEL1 DELAYED VBOOST
VOFF ON
tDEL2 VON VON SLICE START-UP SEQUENCE TIMED BY CDLY FAULT PRESENT
FIGURE 21. ISL97522 START-UP SEQUENCE
17
CHIP DISABLED
VREF ON
DELB ON
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Fault Protection
During the startup sequence, prior to BOOST soft-start, VREF is checked to be within 20% of its final value and the device temperature is checked. If either of these are not within the expected range, the part is disabled until the power is recycled or EN is toggled. If CDELAY is shorted low, then the sequence will not start, while if CDELAY is shorted H, the first down ramp will not occur and the sequence will not complete. Once the start-up sequence is completed, the chip continuously monitors CDLY, DELB, FBP, FBL, FBN, VREF and FBB for faults. During this time, the voltage on the CDLY capacitor remains at 1.15V until either a fault is detected, or the EN pin is pulled low. A fault on CDELAY, VREF or temperature will shut down the chip immediately. If a fault on any other output is detected, CDELAY will ramp up linearly with a 5A (typical) current to the upper fault threshold (typically 2.4V), at which point the chip is disabled until the power is recycled or EN is toggled. If the fault condition is removed prior to the end of the ramp, the voltage on the CDLY capacitor returns to 1.15V. Typical fault thresholds for FBP, FBL, FBN and FBB are included in the tables. DELB fault threshold is typically 0.6V. CINTB and CINTL have an internal current-limited clamp to keep the voltage within their normal ranges. If they are shorted low, the regulators will attempt to regulate to 0V. If any of the regulated outputs (AVDD, VON, VOFF or VLOGIC) are driven above their target levels the drive circuitry will switch off until the output returns to its expected value. If AVDD and VLOGIC are excessively loaded, the current limit will prevent damage to the chip. While in current limit, the part acts like a current source and the regulated output will drop. If the output drops below the fault threshold, a ramp will be initiated on CDELAY and, provided that the fault is sustained, the chip will be disabled on completion of the ramp. In some circumstances, (depending on ambient temperature and thermal design of the board), continuous operation at current limit may result in the over-temperature threshold being exceeded, which will cause the part to disable immediately. All I/O also have ESD protection, which in many cases will also provide overvoltage protection, relative to either ground or VDD. However, these will not generally operate unless abs max ratings are exceeded.
Component Selection for Start-Up Sequencing and Fault Protection
The CREF capacitor is typically set at 220nF and is required to stabilize the VREF output. The range of CREF is from 22nF to 1F and should not be more than five times the capacitor on CDEL to ensure correct start-up operation. The CDEL capacitor is typically 220nF and has a usable range from 47nF minimum to several microfarads - only limited by the leakage in the capacitor reaching A levels. CDEL should be at least 1/5 of the value of CREF (See above). Note with 220nF on CDEL the fault time-out will be typically 50ms and the use of a larger/smaller value will vary this time proportionally (e.g. 1F will give a fault time-out period of typically 230ms).
Fault Sequencing
The ISL97522 has an advanced fault detection system which protects the IC from both adjacent pin shorts during operation and shorts on the output supplies. A high quality layout/design of the PCB, in respect of grounding quality and decoupling is necessary to avoid falsely triggering the fault detection scheme - especially during start-up. The user is directed to the layout guidelines and component selection sections to avoid problems during initial evaluation and prototype PCB generation.
Over-Temperature Protection
An internal temperature sensor continuously monitors the die temperature. In the event that the die temperature exceeds the thermal trip point of 140C, the device will shut down.
Layout Recommendation
The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF, VDC and VDCP bypass capacitors close to the pins. 3. Minimize the length of traces carrying fast signals and high current. 4. All feedback networks should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point near the main decoupling capacitors.
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6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. A signal ground plane, separate from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for feedback resistor networks (R1, R11, R41) and the VREF capacitor, C25, the CDELAY capacitor C7 and the integrator capacitor C30, C27. 9. Minimize feedback input track lengths to avoid switching noise pick-up.
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ISL97522 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
A D N (N-1) (N-2) B
L38.5x7B (One of 10 Packages in MDP0046) 38 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220)
MILLIMETERS SYMBOL A A1 MIN 0.80 0.00 NOMINAL 0.90 0.02 5.00 BSC 3.50 REF 7.00 BSC 5.50 REF 0.35 0.23 0.40 0.25 0.20 REF 0.50 BSC 38 REF 7 REF 12 REF 0.45 0.27 MAX 1.00 0.05 NOTES 4 6 5 Rev 0 5/06 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the "E" side of the package (or Y-direction). 6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE.
1 2 3
PIN #1 I.D. MARK E
D D2 E E2
2X 0.075 C
L
(N/2) TOP VIEW N LEADS 0.10 M C A B (N-2) (N-1) N b
b
2X 0.075 C
c e N ND NE
L
PIN #1 I.D. 3 1 2 3
(E2)
NE 5 (N/2)
(D2) BOTTOM VIEW
7
7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown.
e C
0.10 C (c) 2
SEATING PLANE 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X"
C
A
(L) A1 N LEADS
SIDE VIEW
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN7445.0 December 13, 2006

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